Anecdote about this summary at the bottom:
> This setup gives you the best of both worlds: ESP-IDF and FreeRTOS manage Wi-Fi, BLE, and system tasks on Core 0, while Core 1 runs your bare-metal Rust code at full speed with zero scheduler interference.
I am doing something somewhat like this, but with separate MCUs instead of separate cores. I flashed Esp-Hosted-MCU onto an ESP-32 (C3, but any including S3 will work). This is official firmware which turns the ESP into a "radio co-processor", so you can treat it like a SPI or UART Wi-Fi/BLE chip.
On another MCU (STM32), I run bare-metal firmware in rust which talks to the radio over SPI. Wi-Fi uses the ESP IDF, and BLE uses standard HCI commands.
> This is official firmware which turns the ESP into a "radio co-processor", so you can treat it like a SPI or UART Wi-Fi/BLE chip.
Kinda funny because the ESP8266 basically started off as a WiFi "co-processor" with AT commands sent over UART. People quickly discovered it had a good amount of power and you could run your entire application on the ESP8266 instead of using it as a co-processor. That led to an explosion in popularity for "makers" because the chip was so cheap and capable for projects at the time, and I think that led to the ESP32 becoming so widely known.
Interestingly, Espressif nowadays does something similar on the ESP32-P4 which is RiscV but doesn't have builtin Wifi/BT. So they tend to pair it with an ESP32-C6 which runs the WiFi stack and firmware that communicates with the P4 using SDIO. Not bare metal though, but similar dual-mcu setup for wifi/bt.
I didn’t know about hosted-MCU! I just started using the ESP-AT firmware for an ESP acting as a radio co-processor on a project at work - do you know how hosted-MCU differs?
I did glance at the readme and get the impression that hosted-MCU works for all compatible ESPs and seems more flexible and powerful, where ESP-AT is for select ESP chips and is more limited.
Yes you can pin it to core 1 whilst pinning all other tasks to core 0. Then will never be interrupted or preempted (except by interrupts created on core 1)
This is a great blog, I love the I Built a WebAssembly Runtime in 5 Days Because I Was Tired of Paying for Cloud Run [1], . You do a great job at showcasing your creativity for solving problems. I can tell that you genuinely got a lot of satisfaction from escaping big cloud FaaS, for literally fun and profit. I need more blogs like this.
On basic microcontrollers, mixing message/command I/O with application threads on the same core often lead to missing incoming commands. So it's relatively normal to separate them to their own core free of application logic.
This is reasonably common - Nordic and ST do this as well on the nrf-53 and STm32WB/L respectively. It's convenient for concurrency, and separation of concerns.
Also, running the network stack on a separate core allows it to be encrypted and signed, so that end users can't (easily) reverse engineer it. Which sucks for those of us who would like to run fully open-source code without binary blobs.
For instance, compare the reference manuals for the STM32WL3R and the STM32WB microcontrollers. The former has a single CPU, and it has almost 250 pages of detailed documentation about exactly how the hardware is controlled at a register level. The latter runs the network stack on an auxiliary CPU, and the manual just has a block diagram and a sentence that says "use our drivers" (which are only available in encrypted format).
12 comments:
ESP32-S3 may be the worse model to run Rust on due to the XTensa cores that makes the toolchain unnecessarily complicated.
The newer model, C3, C6, C5 all have RSIC-V cores which make it a dream to run Rust (basically: rustup target add riscv32imac-unknown-none-elf).
Here is a good introduction: https://kerkour.com/introduction-to-embedded-development-wit...
Very good article!
Anecdote about this summary at the bottom: > This setup gives you the best of both worlds: ESP-IDF and FreeRTOS manage Wi-Fi, BLE, and system tasks on Core 0, while Core 1 runs your bare-metal Rust code at full speed with zero scheduler interference.
I am doing something somewhat like this, but with separate MCUs instead of separate cores. I flashed Esp-Hosted-MCU onto an ESP-32 (C3, but any including S3 will work). This is official firmware which turns the ESP into a "radio co-processor", so you can treat it like a SPI or UART Wi-Fi/BLE chip.
On another MCU (STM32), I run bare-metal firmware in rust which talks to the radio over SPI. Wi-Fi uses the ESP IDF, and BLE uses standard HCI commands.
> This is official firmware which turns the ESP into a "radio co-processor", so you can treat it like a SPI or UART Wi-Fi/BLE chip.
Kinda funny because the ESP8266 basically started off as a WiFi "co-processor" with AT commands sent over UART. People quickly discovered it had a good amount of power and you could run your entire application on the ESP8266 instead of using it as a co-processor. That led to an explosion in popularity for "makers" because the chip was so cheap and capable for projects at the time, and I think that led to the ESP32 becoming so widely known.
Interestingly, Espressif nowadays does something similar on the ESP32-P4 which is RiscV but doesn't have builtin Wifi/BT. So they tend to pair it with an ESP32-C6 which runs the WiFi stack and firmware that communicates with the P4 using SDIO. Not bare metal though, but similar dual-mcu setup for wifi/bt.
I didn’t know about hosted-MCU! I just started using the ESP-AT firmware for an ESP acting as a radio co-processor on a project at work - do you know how hosted-MCU differs?
I did glance at the readme and get the impression that hosted-MCU works for all compatible ESPs and seems more flexible and powerful, where ESP-AT is for select ESP chips and is more limited.
I think you can run a single task on core 1 without interference if you give it the right priority (and disable some things).
Yes you can pin it to core 1 whilst pinning all other tasks to core 0. Then will never be interrupted or preempted (except by interrupts created on core 1)
This is a great blog, I love the I Built a WebAssembly Runtime in 5 Days Because I Was Tired of Paying for Cloud Run [1], . You do a great job at showcasing your creativity for solving problems. I can tell that you genuinely got a lot of satisfaction from escaping big cloud FaaS, for literally fun and profit. I need more blogs like this.
[1]: https://tingouw.com/blog/cloud_notes/badwater_intro#day-5-8m...
Interesting, but giving up an entire core to Wi-Fi and Bluetooth seems wasteful.
On basic microcontrollers, mixing message/command I/O with application threads on the same core often lead to missing incoming commands. So it's relatively normal to separate them to their own core free of application logic.
This is reasonably common - Nordic and ST do this as well on the nrf-53 and STm32WB/L respectively. It's convenient for concurrency, and separation of concerns.
Also, running the network stack on a separate core allows it to be encrypted and signed, so that end users can't (easily) reverse engineer it. Which sucks for those of us who would like to run fully open-source code without binary blobs.
For instance, compare the reference manuals for the STM32WL3R and the STM32WB microcontrollers. The former has a single CPU, and it has almost 250 pages of detailed documentation about exactly how the hardware is controlled at a register level. The latter runs the network stack on an auxiliary CPU, and the manual just has a block diagram and a sentence that says "use our drivers" (which are only available in encrypted format).